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AS5132 360 step (8.5 bit) programmable hi gh speed magnetic rotary encoder www.ams.com revision 1.4 1 - 27 1 general description the AS5132 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360 degrees. it is a system- on-chip, combining integrated hall elements, analog frontend and digital signal processing in a single device. to measure the angle, only a simple two-pole magnet, rotating over the center of the chip is required. the absolute angle measurement provides instant indication of the magnet?s angular position with a resolution of 8.5 bit = 360 positions per revolution. this digital data is available as serial output over the interface and as a pulse width modulated (pwm) signal. an additional u,v,w output can be used for a block commutation for a brushless dc motor. an incremental signal is available as an option. in addition to the angle information, the strength of the magnetic field is also available as a 5-bit code. a software programmable (otp) zero position simplifies assembly as the zero position. the magnet does not need to be mechanically aligned. 2 key features ?? 360o contactless angular position sensing ?? two digital absolute outputs (8.5 bit): - serial interface - pwm output ?? incremental output with adjustable number of pulses ?? bldc output uvw, selectable for 1,2,3,4,5,6 pole pairs ?? supports external pwm clock mode ?? static and dynamic pre-commutation feature ?? user programmable zero position and sensitivity ?? high speed: up to 72,900 rpm ?? direct measurement of magnetic field strength allows exact determination of vertical magnet distance ?? incremental outputs abi quadrature: 90ppr, step direction: 180ppr, fixed pulse width 360ppr ?? 9-bit multi turn counter ?? wide magnetic field input range: 20 ? 80 mt (typical) ?? wide temperature range: -40oc to +150oc ?? thin small pb-free package: ssop 20 ?? fully automotive qualified to aec-q100, grade 0 3 applications the AS5132 is suitable for contactless rotary position sensing, rotary switches (human machine interface), ac/dc motor position control and brushless dc motor position control. figure 1. AS5132 block diagram vddp tc tracking adc & angle decoder otp dio pwm clk prog csn pwm decoder agc mag angle commutation interface u_a v_b w_i vdd5v gnd pre-commutation dir com/inc diag diagnostic test(3:0) zero adder step mode s AS5132 hall array & frontend amplifier absolute serial interface (ssi)
www.ams.com revision 1.4 2 - 27 AS5132 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 3 4.1 pin descriptions.......................................................................................................... .......................................................................... 3 5 absolute maximum ratings .................................................................................................... .................................................. 4 6 electrical characteristics.................................................................................................. ......................................................... 5 6.1 operating conditions...................................................................................................... ...................................................................... 5 6.2 system parameters ......................................................................................................... ..................................................................... 5 6.3 magnet specifications ..................................................................................................... ..................................................................... 5 6.4 programming parameters .................................................................................................... ................................................................ 5 6.5 dc characteristics of digital inputs...................................................................................... ................................................................ 6 6.6 dc characteristics of digital outputs ..................................................................................... .............................................................. 6 6.7 timing characteristics .................................................................................................... ...................................................................... 6 7 detailed description........................................................................................................ .......................................................... 7 7.1 synchronous serial interface (ssi) ........................................................................................ .............................................................. 7 7.1.1 commands of the ssi in normal mode ...................................................................................... ................................................. 9 7.1.2 extended synchronous serial interface mode .............................................................................. ............................................ 10 7.1.3 programming verification ................................................................................................ .......................................................... 13 7.2 pulse width modulation (pwm) output....................................................................................... ....................................................... 14 7.2.1 pwm external clock...................................................................................................... ............................................................ 15 7.3 incremental outputs ....................................................................................................... .................................................................... 16 7.3.1 quadrature a/b output ................................................................................................... ........................................................... 16 7.3.2 step output mode........................................................................................................ .............................................................. 17 7.3.3 pre-commutation function................................................................................................ ........................................................ 17 7.3.4 commutation output uvw .................................................................................................. ...................................................... 18 7.3.5 hysteresis of the incremental outputs................................................................................... .................................................... 19 7.3.6 multi turn counter ...................................................................................................... ............................................................... 20 7.3.7 high speed operation .................................................................................................... ........................................................... 20 7.3.8 propagation delay ....................................................................................................... .............................................................. 20 7.3.9 error detection......................................................................................................... .................................................................. 20 8 application information ..................................................................................................... ...................................................... 21 8.1 physical placement of the magnet .......................................................................................... ........................................................... 21 9 package drawings and markings ............................................................................................... ............................................ 23 9.1 recommended pcb footprint................................................................................................. ........................................................... 24 10 ordering information....................................................................................................... ...................................................... 26
www.ams.com revision 1.4 3 - 27 AS5132 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name pin type description 1 vddp supply supply voltage for the selected pins 1 1. vddp can be customized to the voltage levels of the peripheral circuitry to economize voltage level drivers. 2s digital output step output (8ma, vddp) 3w_i commutation output or incremental output 4v_b 5prog supply programming voltage input 6vss supply ground 7 u_a digital output commutation output or incremental output 8 vdd supply positive supply voltage 9 com / inc digital input / schmitt-trigger selection of the output mode. this pin is also used for external clock mode (vddp) 10 tc analog input test pin. set to low in application 11 test0 analog input /output test pin, selection of output format for incremental or step mode 12 test1 13 test2 14 test3 15 dio bi-directional digital data i/o for serial interface (vddp) 16 csn digital input / schmitt-trigger chip select input (active low) (vddp) 17 clk clock input for serial interface (vddp) 18 dir input signal for the pre-commutation at start-up (vddp) 19 diag digital output / open drain diagnostic output (open drain) 20 pwm digital output pwm output (8ma, vddp) 2 3 4 5 6 7 8 1 vddp AS5132 10 9 17 16 15 14 13 12 11 19 18 20 s u_a vss prog v_b w_i tc com/inc vdd pwm diag test3 dio csn clk dir test0 test1 test2
www.ams.com revision 1.4 4 - 27 AS5132 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 5 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters supply voltage (v dd ) -0.3 7 v except during otp programming dc supply voltage (vddp) 0.3 7 v cannot be higher than vdd+0.3 input pin voltage (v in ) vss-0.5 vdd v input current (latch up immunity), (i scr ) -100 100 ma norm: eia/jesd78 class ii level a electrostatic discharge esd 2 kv norm: jesd22-a114e temperature ranges and storage conditions storage temperature (t strg ) -55 150 oc body temperature (t body ) 260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices? . the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level (msl) 3 represents a maximum floor time of 168h
www.ams.com revision 1.4 5 - 27 AS5132 datasheet - electrical characteristics 6 electrical characteristics t amb = -40oc to 150oc, vdd = 4.5v to 5.5v, all volt ages referenced to vss, unless otherwise noted. 6.1 operating conditions 6.2 system parameters 6.3 magnet specifications 6.4 programming parameters symbol parameter conditions min typ max units v dd positive supply voltage 4.5 5.5 v vddp positive supply voltage periphery 3.0 5.5 v idd operating current no load on outputs. supply current can be reduced by using stronger magnets. 15 22 ma symbol parameter conditions min typ max units n resolution 8.5 bit 1deg t pwrup power up time 4100 s t s tracking rate step rate of tracking adc; 1 step = 1o 5.2 s/step inl cm accuracy centered magnet -2 2 deg within horizontal displacement radius -3 3 t delay propagation delay internal signal processing time 22 s tn transition noise peak-peak 1.41 deg symbol parameter conditions min typ max units b z magnetic input range at die surface 20 80 mt v i magnet rotation speed to maintain locked state 1 1. maximum rotation speed is dependent on the internal time reference. maximum value is calculated with lowest sequence over all operating conditions. 72,900 rpm symbol parameter conditions min typ max units v prog programming voltage static voltage at pin prog 8 8.5 v i prog programming current during programming 100 ma tamb prog programming ambient temperature 0 85 oc t prog programming time 24s v r,prog analog readback voltage during analog readback mode at pin prog 0.5 v v r,unprog 23.5
www.ams.com revision 1.4 6 - 27 AS5132 datasheet - electrical characteristics 6.5 dc characteristi cs of digital inputs cmos inputs com/inc, csn, clk, dio, dir 6.6 dc characteristics of digital outputs cmos outputs s, u_a, v_b, w_i, pwm, dio 6.7 timing characteristics symbol parameter min typ max units note v ih high level input voltage 0.7*vddp vddp v com/inc refer to vdd v il low level input voltage 0 0.3*vddp v i leak input leakage current 1 a symbol parameter min typ max units note v oh high level output voltage vddp-0.5 vddp v pwm and s have 8ma output load, dio has 4ma output load. vdd-0.5 vdd u_a, v_b, w_i have 4ma output load. v ol low level output voltage 0 vss+0.4 v pwm and s have 8ma output load, dio, u_a, v_b, w_i has 4ma output load. cl capacitive load 35 pf symbol parameter conditions min typ max units f clk clock frequency normal operation 5 6 mhz f clkp clock frequency programming during otp programming 200 650 khz t1 chip select to positive edge of clk 15 ns t2 setup time command bit, data valid to positive edge of clk 30 ns t3 hold time command bit, data valid after positive edge of clk 30 ns t4 float time, last command bit to negative edge of clk 30 ns t5 transfer time, negative edge to valid data 30 ns t6 last clk to positive edge csn 30 ns t clk clock period 167 200 ns
www.ams.com revision 1.4 7 - 27 AS5132 datasheet - detailed description 7 detailed description figure 3. typical arrangement of AS5132 and magnet 7.1 synchronous serial interface (ssi) the absolute angle data can be read out over the synchronous serial interface using the pins csn , dio and clk . it is a bidirectional interface therefore a read or write access is possible. the organization of the protocol is byte wise and starts with the command byte fo llowed by the data information. figure 4. read / write serial data transmission figure 4 shows the connection of the AS5132 to a micro controller. depending on the command byte are different access types possible. i n normal mode the number of clocks is equal the number of data bits. micro controller 100nf csn clk dio +5v vdd vss vss vdd vdd vss i/o output output AS5132 vddp * * dio output pin is connected internally to the vddp voltage domain. vdd and vddp can be separately connected too.
www.ams.com revision 1.4 8 - 27 AS5132 datasheet - detailed description figure 5. data organization of the ssi protocol 16-bit data figure 5 shows the organization of the data. the first section is used to setup the operating mode and the address. during write mode t he micro controller drives the data line and generates in addition the csn and clk signal. figure 6 shows this operation. figure 6. ssi timing in write mode figure 7. ssi timing in read mode figure 7 shows the read mode. the first 8 command data bits are written by the microcontroller. after the command data the device takes over the dio line and writes the data information. a high impedance phase must be considered before the device drives the output line. command byte r/ w data msb lsb msb lsb 76543210 0 1 2 3 4 15 14 13 12 11 10 cmd 6 clk csn dio d15 command phase data phase d14 d0 t1 12 3 cmd 7 d1 t clk 8 7 cmd 0 91011 24 23 d13 cmd 5 t2 t3 t6 cmd 6 clk csn dio d15 command phase data phase d14 d0 t1 123 cmd 7 d1 t clk 8 7 cmd 0 91011 24 23 d13 cmd 5 z t2 t3 t4 t5 t6
www.ams.com revision 1.4 9 - 27 AS5132 datasheet - detailed description 7.1.1 commands of the ssi in normal mode note: gray bits can be ignored by the user. gen rst: a hi generates a reset of the AS5132. gen rst must be set to lo after reset. hyst_dis: hysteresis disable. pre_com_dyn <5:0>: absolute dynamic pre-commutation value. depending on the setup of the pole pairs, a mechanical angle offset can be adjusted. the range is 0 to 63 mechanical degrees (lsbs). mt-counter <8:0>: the multiturn counter can be set or read over the interface. en prog: this command with this data enables the access to the otp register in extended mode. otp programming mode is only possible in extended mode with special connection (see figure 11) . ez err: indicates a wrong operation of the otp memory after programming at room temperature. angle <8:0>: absolute angle information with angular true resolution (360 steps). lock adc: indicates a locked adc. an angle value is only valid in case of a locked adc. during sleep mode is the lock adc bit lo. agc <5:1>: automatic gain control value indicates the magnetic field strength. p: parity information of the 15 data bits. odd parity. table 3. read/write interface commands in normal mode command name command data access mode msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 write config 0001_0111 write gen rst hyst dis pre_com_dyn<5:0> mtc2 mtc1 set mt counter 0001_0100 write mt - counter <8:0> en prog 1000_0100 write 0 1 1001010 1 1 1000 0 rd mt counter 0000_0100 read mt - counter <8:0> ez err p rd_angle 0000_0000 read angle <8:0> lock adc agc <5:1> p
www.ams.com revision 1.4 10 - 27 AS5132 datasheet - detailed description 7.1.2 extended synchronous serial interface mode the absolute angle data can be read out over the synchronous serial interface using the pins csn , dio and clk . it is a bidirectional interface therefore a read or write access is possible. the organization of the protocol is byte wise and starts with the command byte fo llowed by the data information. figure 8. connectivity during programming in extended mode figure 9. ssi timing in extended write mode micro controller 100nf csn clk dio +5v vdd vss vss vdd vdd vss i/o output output 8. 0 ? 8.5v prog 10 f 100 n AS5132 vddp* *dio output pin is connected internally to the vddp voltage domain. vdd and vddp can be separately connected too. cmd6 csn d63 command phase extended data phase t1 123 cmd7 t clk 8 7 cmd0 91011 cmd5 t2 t3 t6 d62 d1 d0 12 13 67 68 69 70 72 71 dio dclk
www.ams.com revision 1.4 11 - 27 AS5132 datasheet - detailed description figure 10. timing in extended read mode in extended mode the digital interface requires four clocks per data bit. during this time the device is able to handle interna l signals for special access. note: tst is pre-programed by ams and used for test purpose. table 4. read / write interface commands in extended mode command name command data access mode msb 63 ... 17 16 15 14 13 12 11 10 9 8 ... lsb 0 write otp 0001_1111 ext. write tst<46:0> sensitivity <1:0> ext. clk en pre_com_stat <1:0> uvw <2:0> zero angle <8:0> prog otp 0001_1001 ext. write tst<46:0> sensitivity <1:0> ext. clk en pre_com_stat <1:0> uvw <2:0> zero angle <8:0> read otp 0000_1111 ext. write tst<46:0> sensitivity <1:0> ext. clk en pre_com_stat <1:0> uvw <2:0> zero angle <8:0> read ana 0000_1001 ext. read tst<46:0> sensitivity <1:0> ext. clk en pre_com_stat <1:0> uvw <2:0> zero angle <8:0> cmd6 csn d63 command phase extended data phase t1 123 cmd7 t clk 8 7 cmd0 91011 cmd5 t2 t3 t6 d62 d1 d0 12 13 67 68 69 70 72 71 dio dclk z t4 t5
www.ams.com revision 1.4 12 - 27 AS5132 datasheet - detailed description programming parameters. zero angle <8:0>: zero position value. this value is permanent added to the internal absolute position. use range 0 to 359. uvw <2:0>: setup of the number of pole pairs. in the step mode configurati on, the bit uvw<2> is used to invert the step mode output signa l. ext. clk en: enables the external clk mode for the pwm output. the external clk mode is only possible in commutation mode. the state of the pin com/inc is not considered in this case for mode selection. configuration of the number of pole pairs uvw <2:0> number of pole pairs 000 1 001 2 010 3 011 4 100 5 101 6 110 6 111 6 setup of the sensitivity sensitivity <1:0> sensitivity setting min typ max 0 0 1.6 1.65 1.75 0 1 1.79 1.88 1.98 1 0 2.01 2.11 2.22 1 1 2.23 2.35 2.47 setup parameters for the static pre-commutation pre_com_stat <1:0> static pre-commutation value in mechanical degrees 00 0 01 2 10 4 11 8
www.ams.com revision 1.4 13 - 27 AS5132 datasheet - detailed description figure 11. otp programming connection note: the maximum capacitive load at prog in normal operation should be less than 20pf. however, during programming the capacitors c1+c2 are needed to buffer the programming voltage during current spikes, but they must be removed for normal operation. to overcome this contradiction, the recommendation is to add a diode (4148 or similar) between prog and v dd as shown in figure 11 (special case setup), if the capacitors can not be removed at final assembly. due to d1, the capacitors c1+c2 are loaded with v dd -0.7v at startup, hence not influencing the readout of the internal otp registers. during programming the otp, the diode ensures that no cu rrent is flowing from prog (8v to 8.5v) to vdd (5v). in the standard case (see figure 11) , the verification of a correct otp readout must be done by analog readback. the special case setup provides the analog readback of the otp as well. as long as the prog pin is accessible it is recommended to use standard setup. in case the prog pin is not accessible at final assembly, the special setup is recommended. 7.1.3 programming verification after programming, the programmed otp bits must be verified using the following methods: digital read out (mandatory): after sending a read otp command, the readback information must be the same as programmed information. otherwise, it indicates that the programming was not performed correctly. note: either ?digital verification? or ?analog verification? must be carried out in addition to the ?digital read out?. digital verification: checking the ez err bit (0 = ok, 1 = error) i) at room temperature ii) right after the programming analog verification: by switching into extended mode and sending a read ana command, the pin prog becomes an output sending an analog voltage with each clock representing a sequence of the bits in the otp register (starting with d61). a voltage of <500mv indicates a correctly programmed bit (?1?) while a voltage level between 2v and 3.5v indicates a correctly unprogrammed bit (?0?). any volt age level in between indicates incorrect programming. v dd v supply prog gnd c1 c2 100nf 10f v zapp v prog prom cell maximum parasitic cable inductance l<50nh standard case v dd v supply prog gnd c1 c2 100nf 10f v zapp v prog prom cell l<50nh special case remove for normal operation
www.ams.com revision 1.4 14 - 27 AS5132 datasheet - detailed description figure 12. analog otp verification 7.2 pulse width modul ation (pwm) output the AS5132 provides a pulse width modulated output (pwm), whose duty cycle is proportional to the absolute angle position. figure 15 shows the output format. in case of an internal error the high pulse contains 12 steps. an error can be easily identified by the exte rnal microcontroller. the zero degree angle position is build with 16 steps (12 + 4) high and 359 steps low followed by 8 exit steps. figure 13. pwm output +5v vdd AS5132 micro controller vdd csn clk dio vss vss 100nf vss vdd i/o output output prog v vddp * +5v vdd AS5132 micro controller vdd pwm vss vss 100nf vss vdd input vddp * * pwm output pin is connected internally to the vddp voltage domain. vdd and vddp can be separately connected.
www.ams.com revision 1.4 15 - 27 AS5132 datasheet - detailed description 7.2.1 pwm external clock the pwm period depends on the setting of the otp bit ext. clk en . by default the internal clock source is used as a reference. an external clock can be connected to the pin com/inc. in case ext. clk en is set, the output-mode which is determined by the states of {com/inc, test3, test2, test1, test0} (see table 6) during start-up is overwritten and u,v,w commutation mode signals are activated. after internal power on reset (por_en), the otp is read out. when the ext. clk en is programmed successfully, the com/inc pin i s used as external clock for the pwm block. after 4 clock cycles of ext. clk en, the reset of tadc (tadc_rst) and the pwm block is releas ed. figure 14. start-up procedure the reset for the pwm block is synchronized to the external pwm clock. this ensures a save reset also in case the external cloc k on com/inc is already running during start-up. figure 15. pwm output signal table 5. pwm timing with internal and external clk source symbol parameter min typ max unit note t pwmint pwm period internal 600 750 900 s internal clock source t pwmext pwm period external 383 / clk pwm s external clock provided over com / inc pin clk pwm clock external mode 0 766 khz por_en system_state ext. clk en tadc_rst otp_readout run 258*t clk_sys 4*t clk_sys init (error) zero degree angle position 16 clocks 359 clocks exit 8 clocks t-high t-low
www.ams.com revision 1.4 16 - 27 AS5132 datasheet - detailed description 7.3 incremental outputs two different incremental output modes are possible. quadrature a/b mode and selectable step mode can be selected by the pins test0 , test1 , test2 , test3 and com / inc . note: the pin setting com / inc has priority. in case of a low state the device is exclusively in the commutation mode. not specified states of test3, test2, test1 and test0 in incremental mode will enable t he quadrature a/b/i mode. this configuration is only read once a t startup. it is not recommended to change the state during operation. 7.3.1 quadrature a/b output figure 16. incremental output of the AS5132 figure 16 shows the two-channel quadrature output. the index position is mapped to the absolute mechanical zero position. the phase shif t between channel a and b indicates the direction of the magnet movement. channel a leads channel b at a clockwise rotation of th e magnet (top view) by 90 electrical degrees. channel b leads channel a at a counter-clockwise rotation. table 6. configuration of the incremental output modes com / inc test3 test2 test1 test0 output mode pin assignment 1 0 0 0 0 quadrature a/b/i mode 90 pulses per channel a u_a b v_b i w_i ?0? s 1 0 0 0 1 stepmode 24 pulses and index width 2 ?0? u_a ?0? v_b ?0? w_i s_24_2 s 1 0 0 1 0 stepmode 60 pulses and index width 2 ?0? u_a ?0? v_b ?0? w_i s_60_2 s 1 0 0 1 1 stepmode 90 pulses and index width 2 ?0? u_a ?0? v_b ?0? w_i s_90_2 s 1 0 1 0 0 stepmode 180 pulses and index width 2 ?0? u_a ?0? v_b ?0? w_i s_180_2 s 00000 u,v,w commutation mode (otp setting) u u_a v v_b w w_i ?0? s absolute position a b i 0 1 2 3 359 358 357 356
www.ams.com revision 1.4 17 - 27 AS5132 datasheet - detailed description 7.3.2 step output mode step output mode provides a specific combination of the a incremental signal and the index signal i . the number of pulse can be configured with the input pattern of the test input pins. figure 17. step mode of the AS5132 with different number of pulses 7.3.3 pre-commutation function this feature can be used to optimize the torque characteristic at a certain speed of the bldc motor. the output signals u , v and w can be shifted by a specific number of degrees back and forward. the AS5132 distinguish between the static and dynamic pre commutation value. the static value is similar to an additional zero programming and can be programmed only once. the dynamic value is stored in the i nterface register and can be changed during operation. the pin dir defines if the value of pre-commutation is added or subtracted. the dynamic commutation register will be set to zero after a ro tation change indicated by the external pin dir . due to internal synchronization, the outputs u,v,w will change 3 internal clock cycles after the change of dir input signal. table 7. definition of the pre-commutation direction dir rotation consequence 0 clock wise pre_com values added to absolute angle 1 counter clock wise pre_com values subtracted from absolute angle absolute position step s_ 180 _ 2 0 1 2 3 359 358 357 356 180 12 12 3 179 178 177 176 175 6 5 4 absolute position step s_ 90 _ 2 0 1 2 3 359 358 357 356 1234 90 89 88 87 12 567 absolute position s_ 60 _ 2 0 1 2 3 359 358 357 356 step 12 60 59 3 58 12 4 5 absolute position s_ 24 _ 2 0 1 2 3 359 358 357 356 step 12 24 3 4 5 6 7 8 9 355 354 353 352 10 11 1 2
www.ams.com revision 1.4 18 - 27 AS5132 datasheet - detailed description figure 18. block diagram of the pre-commutation function note: the dynamic pre-commutation is set to zero always if the direction is changed over the pin dir . a new value pre_com_dyn must be written again. the static pre-commutation is always enabled and will shift the output. 7.3.4 commutation output uvw the pre-commutation function is used only at the u,v,w output. figure 19 shows the transition on the outputs u,v,w in case of a two pole pair configuration. the static pre-commutation value was set to 12 degrees. figure 19. uvw output transitions with pre-commutation pc adder stat. dir pc adder dyn. dir tracking adc angle<8:0> dir ssi value pre_com_dyn<6:0> zero angle adder otp value zero_ang<8:0> +/- +/- ssi read angle pwm pwm enc u, v, w abi enc a, b, index uvw enc otp value pre_com_stat<2:0> 0 mech. 0 electr. 30 mech. 60 electr. 60 mech. 120 electr. 90 mech. 180 electr. 120 mech. 240 electr. 150 mech. 300 electr. 180 mech. 0 electr. 210 mech. 60 electr. 240 mech. 120 electr. 270 mech. 180 electr. 300 mech. 240 electr. 330 mech. 300 electr. -12 mech. 0 electr. 18 mech. 60 electr. 48 mech. 120 electr. 78 mech. 180 electr. 108 mech. 240 electr. 138 mech. 300 electr. 168 mech. 0 electr. 198 mech. 60 electr. 228 mech. 120 electr. 258 mech. 180 electr. 318 mech. 300 electr. 288 mech. 240 electr. counter clockwise rotation 12 static pre-commutation clockwise rotation 12 static pre-commutation 0 mech. 0 electr. 30 mech. 60 electr. 60 mech. 120 electr. 90 mech. 180 electr. 120 mech. 240 electr. 150 mech. 300 electr. 180 mech. 0 electr. 210 mech. 60 electr. 240 mech. 120 electr. 270 mech. 180 electr. 300 mech. 240 electr. 330 mech. 300 electr. 12 mech. 0 electr. 42 mech. 60 electr. 72 mech. 120 electr. 102 mech. 180 electr. 132 mech. 240 electr. 162 mech. 300 electr. 192 mech. 0 electr. 222 mech. 60 electr. 252 mech. 120 electr. 282 mech. 180 electr. 342 mech. 300 electr. 312 mech. 240 electr. rotation rotation -12 +12
www.ams.com revision 1.4 19 - 27 AS5132 datasheet - detailed description figure 20. dynamic and static pre-commutation 7.3.5 hysteresis of th e incremental outputs a hysteresis is implemented to get a stable output value at the ssi command and to reduce jitter at the pwm and uvw outputs. at start up the hysteresis counter is at 0, the range is 1 lsb. the hysteresis can be deactivated by setting otp bit hyst_dis . figure 21. hysteresis of the outputs 120 180 2 pole pairs, counter clockwise rotation electrical angle mechanical angle 0 60 180 240 300 60 120 0 2 pole pairs, clockwise rotation electrical angle mechanical angle 0 60 180 240 300 60 120 180 120 0 30 90 120 150 210 240 270 60 0 180 dynamic pre-commutation 0x00 ? 0x3f static pre-commutation 0x00...0x06 dynamic pre-commutation 0x00 ? 0x3f static pre-commutation 0x00? 0x06 0 30 90 120 150 210 240 270 60 180 u v w u v w effect of hysteresis cw rotation ccw rotation 0 magnet position angle output 123456 0 1 2 3 4 5 a n a n -1 0 1 hysteresis counter startup value counter range: 3 lsb
www.ams.com revision 1.4 20 - 27 AS5132 datasheet - detailed description 7.3.6 multi turn counter a 9-bit register is used for counting the magnet?s revolutions. with each zero transition in any direction, the output of a spe cial counter is incremented or decremented. the initial value after reset is 0 lsb. clockwise rotation gives increasing angle values and positi ve turn count. counter clockwise rotation exhibits decreasing angle values and a negative turn count respectively. the counter output can be reset by using command 20 ? set mt counter. it is immediately reset by the rising clock edge of this bit. any zero crossing between the clock edge and the next counter readout changes the counter value. 7.3.7 high speed operation the AS5132 is using a fast tracking adc (tadc) to determine the angle of the magnet. the tadc is tracking the angle of the magn et with cycle time of 2 s (typ. 1.4). once the tadc is synchronized with the angle, it sets the lock bit in the status register. once it is locked, it requires only one cycle [2 s (typ. 1.4)] to track the moving magnet. the AS5132 can operate in locked mode at rotational speeds up to max.72,900 rpm. 7.3.8 propagation delay the propagation delay is the time required from reading the magnetic field by the hall sensors to calculating the angle and mak ing it available on the serial or pwm interface. while the propagation delay is usually negligible on low speeds, it is an important parameter at h igh speeds. the longer the propagation delay, the larger becomes the angle error for a rotating magnet as the magnet is moving while the angle is calculated. the position error increases linearly with speed. 7.3.9 error detection the following errors are detected by the system: ?? lock bit ? the tadc has not yet found a valid angular position ?? agc alarm ? the agc value is 63, magnetic field is too weak by default, lock bit error should activate the error condition at the outputs. the agc alarm is permanently available at the di ag pin. error condition at commutation and incremental outputs: ?? u, v and w outputs all ?0? ?? a, b and i outputs all ?1?
www.ams.com revision 1.4 21 - 27 AS5132 datasheet - application information 8 application information the benefits of AS5132 are as follows: ?? complete system-on-chip, no angle calibration required ?? flexible system solution provides absolute serial, pwm and incremental output formats ?? ideal for applications in harsh environments due to magnetic sensing principle ?? high reliability due to non-contact sensing ?? robust system, tolerant to horizontal misalignment, airgap variations, temperature variations and external magnetic fields ?? external clock mode for pwm output 8.1 physical placem ent of the magnet the best linearity can be achieved by placing the center of the magnet exactly over the defined center of the ic package as sho wn in figure 22 . figure 22. defined ic center and magnet displacement radius the centre of the hall sensor array is shifted by a constant value in x axis indicated by the blue circle. in the application i t is important to refer to this point. y x z pin 1 identification 4 .1 0. 235
www.ams.com revision 1.4 22 - 27 AS5132 datasheet - application information figure 23. vertical cross section of ssop-20 notes: 1. all dimensions in mm. 2. die is slightly off centered.
www.ams.com revision 1.4 23 - 27 AS5132 datasheet - package drawings and markings 9 package drawings and markings the device is available in a 20-lead shrink small outline package. figure 24. package drawings and dimensions notes: 1. dimensions and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. marking: @yywwmzz. @ yy ww m zz sublot identifier last two digits of the manufacturing year manufacturing week plant identifier assembly traceability code symbol min nom max a 1.73 1.86 1.99 a1 0.05 0.13 0.21 a2 1.68 1.73 1.78 b 0.22 0.30 0.38 c 0.09 0.17 0.25 d 6.90 7.20 7.50 e 7.40 7.80 8.20 e1 5.00 5.30 5.60 e - 0.65 bsc - l 0.55 0.75 0.95 l1 - 1.25 ref - l2 - 0.25 bsc - r0.09 - - 0o 4o 8o n20 yywwmzz AS5132 @
www.ams.com revision 1.4 24 - 27 AS5132 datasheet - package drawings and markings 9.1 recommended pcb footprint figure 25. pcb footprint recommended footprint data symbol mm inch a 9.02 0.355 b 6.16 0.242 c 0.46 0.018 d 0.65 0.025 e 6.31 0.248
www.ams.com revision 1.4 25 - 27 AS5132 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 0.11 initial draft 0.18 16 dec, 2010 mub updates across datasheet according to 0.18 specification document. 0.19 17 dec, 2010 updated system parameters , ext. clk en under programming parameters , pre-commutation function . 0.20 22 mar, 2011 added otp programming connection , programming verification , analog otp verification . updated package drawings and markings and ordering information . 0.21 06 apr, 2011 updated programming verification . 0.22 07 apr, 2011 added pwm external clock , updated ordering information . 0.23 27 jul, 2011 updated absolute maximum ratings . 04 aug, 2011 updated key features , dc characteristics of digital inputs , package drawings and markings . 0.24 25 nov, 2011 updated vertical cross section of ssop-20 (page 22) and marking info. added figure 9 , figure 10 . 1.0 30 mar, 2012 ekno datasheet release 1.1 06 sep, 2012 text corrections; updated table 4 1.2 26 mar, 2013 mub vddp pin added in figure 4 and figure 13 , idd max corrected in section 6.1, addded load condition vol/voh in section 6.6 and sentences corrected from 8 steps to 16 steps in section 7.2. 1.3 12 apr, 2013 package marking change, added note in section 6.6 for vol and vddp pin added in figure 8 and figure 12 . 1.4 28 jun, 2013 clarification of the revision history (page 25) in versions 1.2 & 1.3.
www.ams.com revision 1.4 26 - 27 AS5132 datasheet - ordering information 10 ordering information the devices are available as the standard products shown in table 8 . note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 8. ordering information ordering code description delivery form package AS5132-hsst 360 step programmable high speed magnetic rotary encoder tape & reel 20-pin ssop
www.ams.com revision 1.4 27 - 27 AS5132 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipien t or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact

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